The present invention generally relates to floating gate memory devices such as an array of flash memory cells, and relates more particularly to a circuit architecture and method for reading and programming NOR flash arrays to reduce column leakage associated therewith.
As is generally known, in recent years a new category of electrically erasable EPROMs/EEPROMs has emerged as an important non-volatile memory which combines the advantages of EPROM density with EEPROM electrical erasability and are sometimes referred to as xe2x80x9cflashxe2x80x9d EPROM or EEPROM. Flash memory devices typically include multiple individual components formed on or within a substrate. Such devices often comprise a high density section and a low density section. For example, as illustrated in prior art FIG. 1a, a memory device such as a flash memory 10 comprises one or more high density core regions 11 and a low density peripheral portion 12 on a single substrate 13. The high density core regions 11 typically consist of at least one Mxc3x97N array of individually addressable, substantially identical floating-gate type memory cells and the low density peripheral portion 12 typically includes input/output (I/O) circuitry and circuitry for selectively addressing the individual cells (such as decoders for connecting the source, gate and drain of selected cells to predetermined voltages or impedances to effect designated operations of the cell such as programming, reading or erasing).
The memory cells within the core portion 11 are coupled together in a NOR-type circuit configuration, such as, for example, the configuration illustrated in prior art FIG. 1b. Each memory cell 14 has a drain 14a, a source 14b and a stacked gate 14c. 
The NOR configuration illustrated in FIG. 1b has each drain terminal 14a of the transistors within a single column connected to the same bit line (BL). In addition, each flash cell 14 has its stacked gate terminal 14c coupled to a different word line (WL) while all the flash cells in the array have their source terminals 14b coupled to a common source terminal (CS). In operation, individual flash cells may be individually addressed via the respective bit line and word line using peripheral decoder and control circuitry for programming (writing), reading or erasing functions.
Prior art FIG. 1c represents a fragmentary cross section diagram of a typical memory cell 14 in the core region 11 of prior art FIGS. 1a and 1b. Such a cell 14 typically includes the source 14b, the drain 14a, and a channel 15 in a substrate or P-well 16; and the stacked gate structure 14c overlying the channel 15. The stacked gate 14c further includes a thin gate dielectric layer 17a (commonly referred to as the tunnel oxide) formed on the surface of the P-well 16. The stacked gate 14c also includes a polysilicon floating gate 17b which overlies the tunnel oxide 17a and an interpoly dielectric layer 17c overlies the floating gate 17b. The interpoly dielectric layer 17c is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate 17d overlies the interpoly dielectric layer 17c. The control gates 17d of the respective cells 14 that are formed in a lateral row share a common word line (WL) associated with the row of cells (see, e.g., prior art FIG. 1b). In addition, as highlighted above, the drain regions 14a of the respective cells in a vertical column are connected together by a conductive bit line (BL). The channel 15 of the cell 14 conducts current between the source 14b and the drain 14a in accordance with an electric field developed in the channel 15 by the stacked gate structure 14c. 
According to conventional operation, the flash memory cell 14 operates in the following manner. The cell 14 is programmed by applying a relatively high voltage VG (e.g., approximately 10 volts) to the control gate 17d and connecting the source to ground and the drain 14a to a predetermined potential above the source 14b. These voltages generate a vertical and lateral electric field along the length of the channel from the source to the drain. This electric field causes electrons to be drawn off the source and begin accelerating toward the drain. As they move along the length of the channel, they gain energy. If they gain enough energy, they are able to jump over the potential barrier of the oxide into the floating gate 17b and become trapped in the floating gate 17b since the floating gate 17b is surrounded by insulators (the interpoly dielectric 17c and the tunnel oxide 17a). As a result of the trapped electrons, the threshold voltage of the cell 14 increases, for example, by about 2 to 5 volts. This change in the threshold voltage (and thereby the channel conductance) of the cell 14 created by the trapped electrons is what causes the cell to be programmed.
To read the memory cell 14, a predetermined voltage VG that is greater than the threshold voltage of an unprogrammed or erased cell, but less than the threshold voltage of a programmed cell, is applied to the control gate 17d with a voltage applied between the source 14b and the drain 14a (e.g., tying the source 14b to ground and applying about 1-2 volts to the drain 14a). If the cell 14 conducts (e.g., about 50-100 xcexcA), then the cell 14 has not been programmed (the cell 14 is therefore at a first logic state, e.g., a zero xe2x80x9c0xe2x80x9d). Likewise, if the cell 14 does not conduct (e.g., considerably less current than 50-100 xcexcA), then the cell 14 has been programmed (the cell 14 is therefore at a second logic state, e.g., a one xe2x80x9c1xe2x80x9d). Consequently, one can read each cell 14 to determine whether it has been programmed (and therefore identify its logic state).
A flash memory cell 14 can be erased in a number of ways. In one arrangement, a relatively high voltage Vs (e.g., approximately 12-20 volts) is applied to the source 14b and the control gate 17d is held at a ground potential (VG=0), while the drain 14a is allowed to float. Under these conditions, a strong electric field is developed across the tunnel oxide 17a between the floating gate 17b and the source 14b. The electrons that are trapped in the floating gate undergo Fowler-Nordheim tunneling through the tunnel oxide 17a to the source 14b. In another arrangement, applying a negative voltage on the order of minus 10 volts to the control gate, applying 5 volts to the source and allowing the drain to float can also erase a cell. In a further arrangement, applying 5 volts to the P-well and minus 10 volts to the control gate while allowing the source and drain to float erases a cell.
When an array of such cells is erased under these conditions, some of the cells will have lower threshold voltages than others. Consequently, even with the control gate 14c being grounded the cell 14 will always be turned on a small amount which causes column leakage current, thereby preventing the proper reading of any other cell in the column of the array containing this cell. In addition, such a condition makes programing of the other cells in the same column increasingly more difficult. This condition often is referred to as xe2x80x9cbit over-erasexe2x80x9d which is disadvantageous since the data programming characteristics of the memory cell 14 is deteriorated so as to cause endurance failures.
The issue of column leakage is significant because in many arrays 512 flash cells are associated with each bit line (BL). Thus if some or all of the 511 non-selected cells in the bit line are exhibiting leakage, power dissipation increases which is highly disadvantageous in portable applications, for example, in which a battery is used as the power supply. In addition, reading the data associated with the selected cell is more difficult because the current associated with the xe2x80x9cleakyxe2x80x9d cells is also detected and a determination must then be made whether the detected current reflects a xe2x80x9c0xe2x80x9d from a conducting selected cell or instead is really a xe2x80x9c1xe2x80x9d and the detected current simply reflects the cumulative leakage current of the leaky cells.
There is a strong need in the art for a flash memory device structure, architecture and process for manufacture that improves the performance and reliability of the device.
The present invention relates to a circuit architecture and method of reading data or programming data in a flash memory in which column leakage associated with over-erased bits is greatly reduced.
According to one aspect of the present invention, a NOR flash memory architecture is disclosed in which individually selectable source lines are run generally parallel to the word lines (e.g., horizontally). In addition, two memory cells associated with a given bit line are coupled in parallel between the bit line and a unique individually selectable source line, yet are connected to separate word lines. Consequently, when reading a desired memory cell, column leakage only occurs with respect to the xe2x80x9cparallel cellxe2x80x9d and the remaining cells associated with the selected bit line do not experience any column leakage. With such an implementation column leakage is reduced by about three (3) or more orders or magnitude over the prior art. Accordingly, power dissipation associated with column leakage current is greatly reduced and the temperature compensation associated with the column leakage is simplified substantially. Furthermore, the architecture of the present invention operates in a manner which is similar to conventional NOR architecture operation, needs only minimal additional logic, and does not require additional metal layers to implement.
According to one aspect of the present invention, a NOR-type flash memory array architecture is disclosed. The flash memory architecture comprises a plurality of flash memory cells which are electrically organized in a column, wherein a drain terminal of each of the flash memory cells are coupled together and for an array bit line input. Further, the control gate terminal associated with each of the flash cells are coupled to a different word line input. In addition, at least one of the flash cells in the array has a source terminal which is electrically isolated from one or more of the source terminals of the other flash cells in the array. Consequently, when the flash cell having the electrically isolated source terminal is selected, for example, to be read, a leakage current associated with flash cells due to a bit over-erase condition is reduced substantially, thereby decreasing power dissipation and increasing cell read accuracy.
According to another aspect of the present invention, a NOR-type flash memory architecture is disclosed which comprises an Mxc3x97N array of flash memory cells, wherein M represents a number of columns or bit lines, and N represents a number of rows or word lines. In the Mxc3x97N array, each flash memory cell associated with a given bit line has a drain terminal coupled thereto and each flash memory cell associated with the given bit line has a control gate terminal coupled to a different word line input. Furthermore the flash memory cells along the given bit line are separated into pairs, wherein each pair of cells are coupled together in parallel between the bit line input and an individually selectable source line which is coupled to a source terminal of each flash cell in the pair. The individually selectable source lines allow electrical isolation between one pair of flash cells from the other flash cells associated with the same bit line, thereby reducing substantially column leakage during programming and reading.
In accordance with yet another aspect of the present invention, a method of programming a flash memory cell in a flash memory array is disclosed. The method includes identifying a flash memory cell in the array for programming and individually selecting a source line associated with the identified cell, wherein the selected source line is not associated with all of the flash cells in the flash memory array. The bit line associated with the identified flash memory cell is then coupled to a voltage potential to facilitate programming and a programming voltage is coupled to a word line associated with the identified cell.
In accordance with still another aspect of the present invention, a method of reading a flash memory cell in a flash memory array is disclosed. The method includes identifying a flash memory cell in the array for programming and individually selecting a source line associated with the identified cell, wherein the selected source line is not associated with all of the flash cells in the flash memory array. The bit line associated with the identified flash memory cell is then coupled to a voltage potential to facilitate reading and a read voltage is coupled to a word line associated with the identified cell. The current in the associated bit line is then sensed and used to determine whether or not the identified memory cell has been programmed.
In accordance with another aspect of the present invention, a method of programming a NOR type flash cell is disclosed. During programming, one or more of the unselected bit lines are grounded or set at a voltage which is less that the programming voltage of the selected bit line, as opposed to floating all unselected bit lines as is done in the prior art. By setting a voltage of one or more of the unselected bit lines during programming, the source side resistance of the selected cell is reduced, thus providing a larger drain-to-source voltage and consequently a faster programming speed.
According to yet another aspect of the present invention, a flash memory array architecture is disclosed in which two or more flash memory cells associated with a given bit line are coupled together in series between their respective bit line and an individually selectable source line to form a set. Further, the series-connected flash memory cells are coupled to separate word lines. In addition, set pairs of such series-connected flash memory cells associated with a given bit line are coupled in parallel between the bit line and a unique, individually selectable source line. Consequently, when reading a desired memory cell, column leakage only occurs with respect to the xe2x80x9cparallelxe2x80x9d set of cells and the remaining cells associated with a given bit line do not experience any column leakage. Further still, due to the xe2x80x9cparallelxe2x80x9d set of cells that may experience leakage being in series with one another, column leakage is further minimized.
With such an implementation column leakage is reduced by about three (3) or more orders or magnitude over the prior art. Accordingly, power dissipation associated with column leakage current is greatly reduced and the temperature compensation associated with the column leakage is simplified substantially. Furthermore, the architecture of the present invention operates in a manner which is similar to a conventional NOR architecture operation, needs only minimal additional logic, and does not require additional metal layers to implement.
According to another aspect of the present invention, a flash memory array architecture comprises a plurality of bit lines, wherein each of the bit lines comprise a plurality of memory cells associated therewith. The plurality of memory cells associated with a given bit line are configured as sets of two or more series-connected flash memory cells, wherein two sets of such series-connected flash memory cells are coupled together in parallel between a respective bit line and an individually selectable source line. In addition, the flash memory array architecture further comprises a plurality of word lines. Each of the plurality of flash memory cells associated with a bit line is coupled to a respective one of the plurality of word lines.
According to another aspect of the present invention, a first set of series-connected memory cells comprises a first flash memory cell having a drain terminal coupled to the respective bit line, a gate terminal coupled to one of the plurality of word lines, and a source terminal. The set further comprises a second flash memory cell having a drain terminal coupled to the source terminal of the first flash memory cell, a gate terminal coupled to a second one of the plurality of word lines, and a source terminal coupled to the individually selectable source line. When one of the flash memory cells in the set is selected to be read (e.g., the first flash memory cell), a read voltage is applied to the word line associated with the selected cell, and the second flash memory cell has a pass voltage applied to its respective word line, thereby allowing the second flash memory cell to conduct and pass the current associated with the selected flash memory cell for reading.
According to yet another aspect of the present invention, a second set of series-connected flash memory cells, which are coupled in parallel with the first set, have their respective word lines grounded, and the second set of series-connected flash memory cells are the only cells associated with the selected bit line which will contribute to any column leakage. Since the flash memory cells in the second set are connected in series, column leakage associated therewith is further minimized by minimizing leakage to the current associated with the least leaky cell in the set.
According to still another aspect of the present invention, the flash memory array architecture further comprises an address control circuit associated with the array of flash memory cells. The address control circuit is operable to generate a plurality of voltages when a flash memory cell is to be read, and further operable to couple the generated voltages to various portions of the array. For example, the address control circuit is operable to couple a first voltage to the respective bit line and a read voltage to the word line associated with the flash memory cell to be read. In addition, the address control circuit is operable to couple a pass voltage to the word line of the flash memory cell connected in series with the flash memory cell to be read, and couple a second voltage which is less than the first voltage to the word lines of the remaining bit lines and the individually selectable source line associated with the flash memory cell to be read.
In doing so, all sets of flash memory cells associated with a given bit line which are not in parallel with the set of series-connected flash memory cells containing the cell to be read do not contribute to column leakage. Furthermore, the only cells which can possibly contribute to column leakage are coupled in series with one another, thus further minimizing the impact of any such leakage.
In accordance with still another aspect of the present invention, a method of reading such a flash memory array architecture is disclosed. The method includes coupling a bit line associated with a selected flash memory cell to be read to a first voltage (e.g., a supply voltage value). An individually selectable source line associated with the selected flash memory cell is then coupled to a second voltage which is less than the first voltage (e.g., a circuit ground potential). The method further includes coupling a word line associated with the flash memory cell to be read to a read voltage and coupling a word line associated with the flash memory cell which is coupled in series with the selected flash memory cell to be read to a pass voltage in order to allow the current associated with the selected flash memory cell to be detected accurately.
In addition, word lines associated with the parallel set of series-connected flash memory cells (parallel with the set containing the selected flash memory cell) are connected to a third voltage which is less than the first voltage (e.g., a circuit ground potential). Lastly, a current associated with the selected flash memory cell is detected and the current is indicative of a data value associated with the selected flash memory cell.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.